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asynchronous sar adc thesis

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This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

muhammadaldacher/Analog-Design-of-Asynchronous-SAR-ADC

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Analog-design-of-asynchronous-sar-adc.

This project is about the design process of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using 45nm CMOS technology. SAR ADCs are attractive circuits for applications that require low power with medium resolution and medium speed like in computing-in-memory cores for AI applications and in sensors for biomedical applications. The asynchronous architecture allow the ADC to operate without the need for an oversampled clock reducing the design complexities associated with higher frequencies. The top-level block diagram of the asynchronous SAR ADC is shown below, along with the timing diagram of the important signals.

image

1) Internal Clock Generator

The internal clock generator is the block responsible for providing the rest of the system with the clock signals to operate. This block produces 2 output signals, “clk_sample” and “clk_sar”, and receives 3 inputs “clk_ext”, “Ready”, and “EOC”.

2) Bootstrapped Sample-And-Hold Switches

The sample-and-hold circuit is basically a switch that captures the value of an analog signal at a certain moment and holds it constant for a certain amount of time. The bootstrapped switch help mitigate some of the switch non-idealities by keeping the switch’s VGS fixed during the sampling phase.

3) Capacitive DAC

The capacitive DAC uses charge redistribution to convert the digital code coming from the SAR logic into the corresponding analog voltage level to be compared by the comparator.

4) Dynamic Comparator

The comparator’s function is to compare the analog input levels coming from the DAC and to produce a digital output bit (either high or low) representing the result of the comparison. A high-speed low-power strongarm comparator is used.

5) SAR Logic

The SAR logic generates the digital code for the DAC in each comparison stage. At the end of the conversion cycle, the final digital code is outputted by an output register. The flipflops used are TSPC flipflops with asynchronous set and reset inputs.

* Analysis & Results:

image

Key References:

[1] O. Kardonik, "A study of SAR ADC and implementation of 10-bit asynchronous design," M.S. Thesis, Department of Electrical and Computer Engineering, University of Texas at Austin, 2013.

[2] P. J. A. Harpe et al., "A 26 uW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios," IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp. 1585-1595, July 2011.

[3] M. Al-Qadasi, A. Alshehri, A. S. Almansouri, T. Al-Attar, and H. Fariborzi, "A High Speed Dynamic StrongARM Latch Comparator," 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, ON, Canada, 2018, pp. 540-541.

[4] M. Dessouky and A. Kaiser, "Very low-voltage digital-audio Δ∑ modulator with 88-dB dynamic range using local switch bootstrapping," IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 349-355, March 2001.

For more info, check the project's report & ppt: https://github.com/muhammadaldacher/Analog-Design-of-Asynchronous-SAR-ADC/blob/main/%5BReport%5D%20Design%20of%20a%20Low-Power%20Asynchronous%20SAR%20ADC%20in%2045%20nm%20CMOS%20Technology.pdf

https://github.com/muhammadaldacher/Analog-Design-of-Asynchronous-SAR-ADC/blob/main/%5BPPT%5D%20Design%20of%20a%20Low-Power%20Asynchronous%20SAR%20ADC%20in%2045%20nm%20CMOS%20Technology.pdf

My project on google drive: https://drive.google.com/drive/folders/1zEzuneabBBtgcV0V-nYb4Kvp_cLarDpZ?usp=sharing

Carnegie Mellon University

SAR ADCs Design and Calibration in Nano-scaled Technologies

The rapid progress of scaling and integration of modern complimentary metal oxide semiconductor (CMOS) technology motivates the replacement of traditional analog signal processing by digital alternatives. Thus, analog-to-digital converters (ADCs), as the interfaces between the analog world and the digital one, are driven to enhance their performance in terms of speed, resolution and power efficiency. However, in the presence of imperfections of device mismatch, thermal noise and reduced voltage headroom, efficient ADC design demands new strategies for design, calibration and optimization. Among various ADC architectures, successive-approximation-register (SAR) ADCs have received renewed interest from the design community due to their low hardware complexity and scaling-friendly property. However, the conventional SAR architecture has many limitations for high-speed, high-resolution applications. Many modified SAR architectures and hybrid SAR architectures have been reported to break the inherent constraints in the conventional SAR architecture. Loop-unrolled (LU) SAR ADCs have been recognized as a promising architecture for high-speed applications. However, mismatched comparator offsets introduce input-level dependent errors to the conversion result, which deteriorates the linearity and limits the resolution and the resolution of most reported SAR ADCs of this kind are limited to 6 bits. Also, for high-resolution SAR ADCs, the comparator noise specification is very stringent, which imposes a limitation on ADC speed and power-efficiency. Lastly, capacitor mismatch is an important limiting factor for SAR ADC linearity, and generally requires dedicated calibration to achieve efficient designs in terms of power and area. In this work, we investigate the impacts of offset mismatch, comparator noise and capacitor mismatch on high-speed SAR ADCs. An analytical model is proposed to estimate the resolution and predict the yield of LU-SAR ADCs with presence of comparator offset mismatch. A background calibration technique is proposed for resolving the comparator mismatch issue. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7-dB to 42.9-dB. The ADC consumes 640 μW from a 1.2 V supply with a Figure-of-Merit (FoM) of 37.5-fJ/conv-step. Moreover, the bit-wise impact of comparator noise is studied for LU-SAR ADCs. Lastly, an extended statistical element selection (SES) calibration technique is proposed to calibrate the capacitor mismatch in SAR ADCs. Based on these techniques, a high-resolution, asynchronous SAR architecture employing multiple comparators with different speed and noise specifications to optimize speed and power efficiency. A 12-bit prototype ADC is fabricated in a 1P9M 65nm CMOS technology, and fits into an active area of 500 μm × 200 μm. At 125 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 64.4 dB and a spurious-free-dynamic-range (SFDR) of 75.1 dB at the Nyquist input frequency while consuming 1.7 mW from a 1.2 V supply. The resultant figure-of-merit (FoM) is 10.3 fJ/conv-step.

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  • Dissertation
  • Electrical and Computer Engineering

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  • Doctor of Philosophy (PhD)

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A study of SAR ADC and implementation of 10-bit asynchronous design

  • Olga Kardonik
  • Published 1 August 2013
  • Engineering, Computer Science

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Split-sar adcs: improved linearity with power and speed optimization, sar adc architecture with 98% reduction in switching energy over conventional scheme, a 26 $\mu$ w 8 bit 10 ms/s asynchronous sar adc for low energy radios, 500-ms/s 5-bit adc in 65-nm cmos with split capacitor array dac, a 15fj/conversion-step 8-bit 50 ms/s asynchronous sar adc with efficient charge recycling technique, a 9-bit 50ms/s asynchronous sar adc in 28nm cmos, design of a 12-b asynchronous sar cmos adc, related papers.

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A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC

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Issue Date 2018
Abstract High-speed high-precision analog-to-digital converters (ADCs) are widely used in the fields of image processing, information storage and wireless communication. To achieve high speed and high precision, relative to other structures, a pipeline-architecture ADC has an advantage: it can take both accuracy and speed into account. With the continuous improvement of integrated circuits (IC) manufacture process, the speed limit of the circuit is getting higher and higher. At the same time, however, the process dimension is getting smaller and smaller, with the supply voltage becoming ever lower, which makes it hard for the operational amplifier (op-amp) to achieve high gain. What’s more, the power consumption is usually high because there are many stages in a pipelined ADC, and a power hungry op-amp is needed in each stage. So pipelined-successive-approximation-register (SAR) ADCs have been introduced to solve this problem. Using an SAR ADC as the sub-ADC in a pipelined ADC instead of a flash ADC can significantly reduce the system complexity. Usually only two stages and one op-amp are needed for a pipelined-SAR ADC, which gives this architecture a high power efficiency. But the sampling speed is limited as an SAR ADC takes much more time to do the quantization than a flash ADC. So the settling time for a multiplying-digital-to-analog-converter (MDAC) is even less. Another issue is that the higher the first-stage resolution is, the larger the gain bandwidth (GBW) requirement is. So for a 5- or 6-bit first stage, it is not easy to design a high-speed closed-loop MDAC to meet the requirement. In this work, a pipelined-SAR is designed with an open-loop MDAC. To achieve high speed, an open-loop low-gain and high-bandwidth op-amp is used in the MDAC, and the power-hungry high-gain high-bandwidth amplifier is cancelled to save power. The gain is calibrated in the foreground using a parasitic capacitor array at the MDAC input. To push the sampling speed even higher, separate digital-to-analog-converter (DAC) arrays are used for the MDAC and sub-ADC to reduce the first-stage SAR ADC bit-cycling time constant in order to compress the quantization time. A loop-unrolled asynchronous SAR ADC is used to speed up the sub-ADC further. This architecture uses n comparators for an n-bit ADC. The outputs of the comparators can be directly given to the SAR DAC array without any extra logic and there is also no need for the comparators to do the reset within one conversion period. In this way the SAR logic delay is cancelled. But for this multiple comparators design, the comparator offsets need calibration. The offsets’ values will vary with the input common-mode voltage, so background calibration is used to calibrate the offsets at the corresponding common-mode voltage. Next, a 12-bit 400-MS/s single-channel pipelined-SAR ADC is implemented using a UMC 65-nm CMOS process with 1.3-V supply voltage. The chip includes a reference buffer, low jitter clock receiver and low-voltage differential signaling (LVDS) output driver. Large decoupling capacitors are used in the ADC chip. The total area of the chip including the pads is 1.875x1.875 mm with a core area of 0.5 mm x 1.1 mm. The measurement results show that the ADC core consumes 12.5 mW power (the reference buffer, clock buffer and LVDS output driving power are not included). The testing speed is limited to 300 MS/s due to the equipment restriction (logic analyzer). So the power supply is reduced to 1.2-V during testing. After the foreground gain calibration, the signal-to-noise and distortion ratio (SNDR) is 63.55 dB and the spurious free dynamic range (SFDR) is 79.15dB for 10-MHz input. The design achieves a figure of merit (FoM) of 34 fJ/conv-step.
Note Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2018
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A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS

  • Published: 21 January 2021
  • Volume 40 , pages 3125–3142, ( 2021 )

Cite this article

asynchronous sar adc thesis

  • Mengying Hu 1 ,
  • Jing Jin   ORCID: orcid.org/0000-0003-3584-5559 1 ,
  • Yuekang Guo 1 ,
  • Xiaoming Liu 1 &
  • Jianjun Zhou 1  

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4 Citations

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This paper presents a power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) with fast response reference buffer (RV-buffer). Several techniques are applied in the system design to improve the performance of the SAR ADC. A novel timing-redistribution SAR logic is proposed to balance the difference between required settling time for the most significant bit and the least significant bits (LSBs) in the digital-to-analog capacitor array, which reduces the incomplete settling error and releases the requirements on the RV-buffer to achieve lower power dissipation. The SAR ADC is fabricated in 40-nm CMOS technology occupying 0.13 mm \(^{2}\) area. At 1.1 V supply voltage and 80 MHz sampling frequency, the ADC achieves 50.7 dB SNDR, 69.5 dBc SFDR with a 1 MHz input at −8 dBFS. The total power consumption of the ADC is 2.99 mW, including the reference buffer power consumption of 2 mW. The Schreier FoM is 164.1 dB.

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Acknowledgements

We would like to thank the Chinese National Nature Science Foundation (No. 61974092) for funding this research.

Chinese National Nature Science Foundation (No. 61974092)

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Hu, M., Jin, J., Guo, Y. et al. A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS. Circuits Syst Signal Process 40 , 3125–3142 (2021). https://doi.org/10.1007/s00034-020-01643-z

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Received : 03 August 2020

Revised : 23 December 2020

Accepted : 24 December 2020

Published : 21 January 2021

Issue Date : July 2021

DOI : https://doi.org/10.1007/s00034-020-01643-z

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  • Huang Y Huang L Wu J (2021) An energy-efficient switching scheme based on the improved semi-resting DAC structure and floating-capacitor technique for SAR ADC Analog Integrated Circuits and Signal Processing 10.1007/s10470-021-01910-2 108 :3 (679-687) Online publication date: 1-Sep-2021 https://dl.acm.org/doi/10.1007/s10470-021-01910-2
  • Ghoshal P Dey C Sen S (2021) Realization of an ultra low power and area efficient SC SAR ADC architecture using single and two step reset methods Microsystem Technologies 10.1007/s00542-020-05118-8 27 :9 (3571-3577) Online publication date: 1-Sep-2021 https://dl.acm.org/doi/10.1007/s00542-020-05118-8
  • Li J Li X Huang L Wu J (2020) An energy-efficient switching scheme with low common-mode voltage variation and no-capacitor-splitting DAC for SAR ADC Analog Integrated Circuits and Signal Processing 10.1007/s10470-020-01661-6 104 :1 (93-101) Online publication date: 11-May-2020 https://dl.acm.org/doi/10.1007/s10470-020-01661-6

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Analysis of the second-order ns sar adc performance enhancement based on active gain.

asynchronous sar adc thesis

1. Introduction

2. mathematical analysis of previous second-order fully-passive ns sar adc, 3. the proposed second-order ns sar adc, 3.1. the second-order ns sar adc based on active gain, 3.2. improved second-order ns sar adc based on active gain, 3.3. the values of a and δt/τ, 3.4. improved sampling speed, 3.5. kickback noise, 4. performance comparison, 5. conclusions, author contributions, data availability statement, conflicts of interest.

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Click here to enlarge figure

ArchitectureSecond-Order Fully-Passive NS SARNS SAR Based on Active GainImproved NS SAR Based on Activegain
C largemediumsmall
ADC Input Cap
kT/C Suppressed?×√√
Comparator Noise Suppressed?√√√
Extra Cycles?√××
Static Power×√√
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Share and Cite

Jia, S.; Ye, T.; Xiao, S. Analysis of the Second-Order NS SAR ADC Performance Enhancement Based on Active Gain. Electronics 2024 , 13 , 3400. https://doi.org/10.3390/electronics13173400

Jia S, Ye T, Xiao S. Analysis of the Second-Order NS SAR ADC Performance Enhancement Based on Active Gain. Electronics . 2024; 13(17):3400. https://doi.org/10.3390/electronics13173400

Jia, Shichao, Tianchun Ye, and Shimao Xiao. 2024. "Analysis of the Second-Order NS SAR ADC Performance Enhancement Based on Active Gain" Electronics 13, no. 17: 3400. https://doi.org/10.3390/electronics13173400

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IMAGES

  1. 4 -Time chart of synchronous and asynchronous SAR ADCs.

    asynchronous sar adc thesis

  2. Analog Design Of Asynchronous Sar Adc

    asynchronous sar adc thesis

  3. Sensors

    asynchronous sar adc thesis

  4. (PDF) Masters Dissertation: Design of a low-power 10-bit 12-MS/s

    asynchronous sar adc thesis

  5. Figure 1 from A 10-bit 20-MS/s Asynchronous SAR ADC using Self

    asynchronous sar adc thesis

  6. Analog Design Of Asynchronous Sar Adc

    asynchronous sar adc thesis

VIDEO

  1. SATVIK TWINS is 🔥 #freefire

  2. Voltage sag compensation using STATCOM for asynchronous motor

  3. Voltage sag compensation using STATCOM for asynchronous motor Matlab Simulation Assignment

  4. Conversion process of a SAR-ADC

  5. Asynchronous machine Direct torque Control Matlab Simulation

  6. ASYNCHRONOUS FIFO SIMULATION DEMO

COMMENTS

  1. PDF Design of High-speed, High-resolution Sar A/D

    AR ADC was designed and fabricated as a proof of concept for these design techniques.Finally, we investigated the concept of SAR-pipelining as a viable option to realize moderate. o high resolution (> 65 dB SNDR), high-speed (> 150 MS/s), low energy A/D converters. A mod.

  2. muhammadaldacher/Analog-Design-of-Asynchronous-SAR-ADC

    The top-level block diagram of the asynchronous SAR ADC is shown below, along with the timing diagram of the important signals. ... "A study of SAR ADC and implementation of 10-bit asynchronous design," M.S. Thesis, Department of Electrical and Computer Engineering, University of Texas at Austin, 2013. [2] P. J. A. Harpe et al., "A 26 uW 8 bit ...

  3. A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS

    In this work, an asynchronous implementation of the SAR ADC was employed. Typical synchronous implementations [] make use of two synchronized clock sources, one to control the data sampling (the sampling clock) and other to control the converter iterations (the SAR iteration clock).On the other hand, asynchronous SAR ADCs [7, 8] require only one clock signal to control the sampling.

  4. PDF Low-Power High-Performance SAR ADC with Redundancy and Digital

    step FoM. This ADC achieves the best FoM of any ADCs with greater than 10b ENOB and 10MS/s sampling rate. Thesis Supervisor: Duane S. Boning Title: Professor of Electrical Engineering and Computer Science Thesis Supervisor: Hae-Seung Lee Title: Professor of Electrical Engineering and Computer Science 3

  5. PDF A 12-bit SAR ADC for a flexible tactile sensor

    The proposed ADC is aimed at a tactile sensor application, requiring a low-noise and low-power solution. In addition, it should have high SNDR to detect even the weakest signals with precision. This thesis presents a 12-bit 400 kS/s SAR ADC implemented in a 180 nm CMOS technology for such a task.

  6. Masters Dissertation: Design of a low-power 10-bit 12-MS/s asynchronous

    ADC. ThesisPDF Available. Masters Dissertation: Design of a low-power 10-bit 12-MS/s asynchronous SAR ADC. September 2020. DOI: 10.11606/D.18.2020.tde-16122021-162821. Thesis for: Master of ...

  7. SAR ADCs Design and Calibration in Nano-scaled Technologies

    A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7-dB to 42.9-dB. The ADC consumes 640 μW from a 1.2 V supply with a Figure-of-Merit (FoM) of 37.5-fJ/conv-step. Moreover, the bit-wise impact of comparator noise is studied for ...

  8. Design and Simulation of 1 0- Bit SAR ADC Using 18nm FinFET Technology

    This paper presents a cutting-edge 1.2V 10-bit asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) meticulously designed and simulated in the advanced 18 nm FinFET CMOS technology. This asynchronous SAR ADC system consists of an internal-clock generator, switching unit, fully differential pair of capacitive Digital-to-Analog Converter (DAC), a dynamic ...

  9. Design and simulation of a 12-bit, 40 MSPS asynchronous SAR ADC for the

    Key words: SAR ADC, asynchronous SAR logic, bootstrapped switch, dynamic comparator, LHAASO, WCDA PACS: 84.30.-r, 07.05.Hd 1 Introduction The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for high energy gamma ray and cosmic ray detection [1-3]. One of the major components is the Water Cherenkov Detector Array

  10. Design and Analysis of SAR-ADC for Low Power Circuits

    This paper introduces an innovative concept centered on developing an 8-bit Asynchronous Successive Approximation Register (SAR) Analog to Digital Converter (ADC) utilizing state-of-the-art 18nm FinFET technology. This advanced asynchronous SAR system encompasses multiple crucial components, including a precisely engineered internal clock generator, a high-performance bootstrapped sample and ...

  11. A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for ...

    A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed.

  12. Design of a low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS

    D. Zhang, Design of Ultra-Low-Power Analog-to-Digital Converters, Linköping: PhD Thesis, 2012. Google Scholar; A. M. Abo and P. R. Gray, "A 1.5-V, ... Design of a low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS. Hardware. Integrated circuits. Very large scale integration design. Analog and mixed-signal circuits.

  13. A Systematic Design Methodology of Asynchronous SAR ADCs

    Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in biomedical and portable/wearable electronic systems due to their excellent power efficiency. However, both the design and the optimization of high-performance SAR ADCs are time consuming, even for well-experienced circuit designers. For system designers, it is also hard to quickly evaluate the ...

  14. PDF Design Techniques for Ultra-High-Speed Time-Interleaved Analog-to

    1.1 Thesis organization 3 2. High-speed sampling 4 2.1 Track-and-hold circuits 4 ... asynchronous SAR ADC with 400mV input swing and 1.05V supply 34 3.8 Waveform of a classic asynchronous SAR ADC in the scenario that (a) a meta-stability event does not cause a sparkle-code and (b) a meta-stability event caused a sparkle-code 35 ...

  15. A study of SAR ADC and implementation of 10-bit asynchronous design

    A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios. The fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6 nW and the energy efficiency of this converter can be maintained down to very low sampling rates.

  16. A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC

    A loop-unrolled asynchronous SAR ADC is used to speed up the sub-ADC further. This architecture uses n comparators for an n-bit ADC. The outputs of the comparators can be directly given to the SAR DAC array without any extra logic and there is also no need for the comparators to do the reset within one conversion period. ... Thesis (Ph.D ...

  17. A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for ...

    A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching ...

  18. PDF Time-interleaved SAR ADC Design Using Berkeley Analog Generator

    First, a 9-bit 16-way time-interleaved SAR ADC core including decoupling capacitor and voltage references are fully generated by the generator. It works at sampling rate 10GS/s and simulated SNDR is 37.6 dB at Nyquist frequency. In order to set the con guration bits and read out quantized result.

  19. Asynchronous vs Synchronous SAR ADCs

    This paper presents a comparison between a Itl-bit asynchronous SAR (ASAR) ADC and a 10-bit synchronous SAR (SSAR) ADC, both designed and simulated in a 22-nm FDSOI CMOS process. To further support the simulation results, the ASAR ADC has also been fabricated and measurements are pre-sented. As opposed to the abrupt SNDR collapse in the SSAR ADC, the SNDR of the ASAR ADC shows a more graceful ...

  20. PDF Asynchronous SAR ADC: Past, Present and Beyond

    Low-power, high-speed ADCs are in great needs. New opportunities and breakthroughs are expected in accelerated rate. Asynchronous SAR ADC architecture provides power efficient platform for achieving this goal. The record high-speed (90GS/s) ADC also leverages this topology.

  21. A Power-Efficient SAR ADC with Optimized Timing ...

    This paper presents a power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) with fast response reference buffer (RV-buffer). Several techniques are applied in the system design to improve the performance of the SAR ADC. A novel timing-redistribution SAR logic is proposed to balance the difference between required settling time for the most significant bit ...

  22. Design of a low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS

    This work presents the design and implementation of a low power successive approximation register analog-to-digital converter (SAR ADC) in a 65nm CMOS technology, suitable for low power frontend of wireless receivers with a flexible sampling rate up to 12 MS/s.

  23. A 17 MS/s SAR ADC with energy-efficient switching strategy

    A study of SAR ADC and implementation of 10-Bit asynchronous design. A thesis submitted to the University of Texas at Austin for the degree of Master of Science in Engineering. ... Wen, J. Y., Chang, P. H., Huang, J. F., & Lai, W. C. (2015). Chip design of a 12-bit 5MS/s fully differential SAR ADC with resistor-capacitor array DAC technique for ...

  24. Low power design of asynchronous SAR ADC

    In this paper 8 bit SAR ADC with input voltage of 1.2V has been designed. The schematic diagram of different sub blocks has been implemented in Cadence Virtuoso using 180nm technology. Comparator was designed so that it remains in saturation for proper operation and was implemented using differential amplifier. The comparator is the main power consuming block, so most of our effort was focused ...

  25. Electronics

    This paper presents a novel second-order passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) based on active gain. The proposed scheme achieves a further improvement in the signal-to-noise ratio (SNR) of the proposed NS SAR ADC by reducing the kT/C noise and the conversion rate. After having presented the conversion principle, the theoretical ...