assignment must have a variable data type

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Procedural Assignment error (verilog )

• Thread starter vead
• Start date Sep 23, 2014
• Sep 23, 2014

Full Member level 5

hello , when i compile code I am getting following error line if (ld==1) q4 <= d4; Error (10137): Verilog HDL Procedural Assignment error at core_v.v(70): object "q4" on left-hand side of assignment must have a variable data type Code: module core_v(clk,ld,d0, q0,d1,d2,q1,q2,a,b,z,sel,d,q,d3,q3,d4,q4 ); input clk; input ld; reg [3:0] q0; reg [3:0] q1; reg [3:0] q2; reg [3:0] z; //add r0 core_v core_vr0 ( d0, q0); input [3:0] d0; output q0; always @(posedge clk) begin if (ld==1) q0 <= d0; end // add r1 core_v core_vr1 ( d1, q1); input d1; output q1; always @(posedge clk) begin if (ld==1) q1 <= d1; end //add r2 core_v core_vr2_i ( d2, q2); input d2; output q2; always @(posedge clk) begin if (ld==1) q2 <= d2; end // add acc core_v core_vacc( d, q); input d; output q; reg [3:0] q; always @(posedge clk) begin if (ld==1) q <= d; end //add temacc core_v core_tempacc(d3,q3 ); input d3; output q3; always @(posedge clk) begin if (ld==1) q <= d; end // add accreg core_v core_tempreg(clk, ld, d4, q4); input d4; output q4; always @(posedge clk) begin if (ld==1) q4 <= d4; end //add alu core_v core_alu (z,a,b,sel); input a, b; input sel; output z; always@(sel,a,b) begin case(sel) 4'b0000: z=a+b; 4'b0001: z=a-b; 4'b0010: z=b-1; 4'b0011: z=a*b; 4'b0100: z=a&&b; 4'b0101: z=a||b; 4'b0110: z=!a; 4'b0111: z=~a; 4'b1000: z=a&b; 4'b1001: z=a|b; 4'b1010: z=a^b; 4'b1011: z=a<<1; 4'b1100: z=a>>1; 4'b1101: z=a+1; 4'b1110: z=a-1; endcase end endmodule how to remove this error  

Advanced Member level 3

It would really help if you would declare your ports using the syntax added by Verilog-2001. It is 2014 after all. How did you declare "q4".  

dave_59 said: It would really help if you would declare your ports using the syntax added by Verilog-2001. It is 2014 after all. How did you declare "q4". Click to expand...

Full Member level 6

What exactly are you trying to do here? This code makes no sense. You have declared a module called core_v, inside of which you are instantiating copies of core_v (which you can't do) and doing it incorrectly anyway as you are not listing all the ports of core_v. And then you intersperse these instantiations with some Verilog code. I am guessing that what you are trying to do is create a module called core_v which instantiates other submodules which contain various functions. But this is certainly not the way to do it. You need to get yourself a Verilog book and find some proper examples of this. Assuming this is what you want to do. r.b.  

look the diagram 2.13 I want write verilog code for that circuit **broken link removed** - - - Updated - - - http://msxarchive.nl/pub/msx/mirrors/msx2.com/zaks/z80prg02.htm  

I don't want to retype what is easily found on the web already, so here is a link that shows how to write a module that instantiates other modules. As for the diagram, you as the designer will have to decide how you want to divide up the functionality. If it is a small amount of code, you might just write all of it in the main module and dispense with sub-modules. Or make the register block a sub-module and write the rest directly in the main module. Or any other way you feel is useful to you. r.b.  

• Sep 24, 2014

rberek said: I don't want to retype what is easily found on the web already, so here is a link that shows how to write a module that instantiates other modules. As for the diagram, you as the designer will have to decide how you want to divide up the functionality. If it is a small amount of code, you might just write all of it in the main module and dispense with sub-modules. Or make the register block a sub-module and write the rest directly in the main module. Or any other way you feel is useful to you. r.b. Click to expand...

TrickyDicky

Advanced member level 7.

The error comes because you are instantiating the adder_implicit module inside itself, giving infinite recursion.  

TrickyDicky said: The error comes because you are instantiating the adder_implicit module inside itself, giving infinite recursion. Click to expand...

You are still not getting it. What is u0 supposed to do be doing? Unfortunately, that website I pointed you to does not show the best example of writing a module. I should have looked closer. Here is a super simple Verilog module: Code: module blah ( input wire a, input wire b, output wire c ); assign c = a | b; endmodule You do not need to instantiate a module inside itself as you have been trying to do. r.b.  

rberek said: You are still not getting it. What is u0 supposed to do be doing? Unfortunately, that website I pointed you to does not show the best example of writing a module. I should have looked closer. Here is a super simple Verilog module: Code: module blah ( input wire a, input wire b, output wire c ); assign c = a | b; endmodule You do not need to instantiate a module inside itself as you have been trying to do. r.b. Click to expand...

What are you trying to do with that code? What did you think it would do? Is it supposed to be an instantiation of something? Its not legal Verilog as far as I know, so if you tell us what this was trying to achieve, maybe we can help. r.b.  

Super Moderator

Go back and look at rberek's link in #6 Your code: Code: // Code Starts Here u0( r1[0] , r2[0] , ci , result[0] , c1 ); is incorrectly written compared to the example in #6. Code: // Code Starts Here [B][I][COLOR="#FF0000"]addbit[/COLOR][/I][/B] u0( r1[0] , r2[0] , ci , result[0] , c1 ); You need to compile the addbit.v module first, so when you compile the adder_implicit module it can find something to fill the spot for u0. BTW implicit ordering of ports on an instantiated module is NOT recommended. It is better to use named ordering of the ports. i.e. .port_name (port_connection_name), ... You should read a book on Verilog, instead of flailing around trying to learn Verilog from poorly written website tutorials. I initially learned Verilog using the Thomas/Moorby book and later bought Verilog HDL by Palnitkar. I only use websites as a quick reference.  

ok i want to write code for following example there are three registers that are connected with single data bus I have written code but getting error Code: module register (clk, ld, d0,d1,d2,q0,q1,q2); input clk; input ld; // Input Port Declarations input [3:0] d0 ; input [3:0] d1 ; input [3:0] d2 ; // Output Port Declarations output [3:0] q0; output [3:0] q1; output [3:0] q2; // ports wire wire [3:0] c0; wire [3:0] c1; wire [3:0] c2; reg [3:0]q0; always @(posedge clk) begin if (ld==1) q0 <= d0; end reg [3:0]q1; always @(posedge clk) begin if (ld==1) q1 <= d1; end reg [3:0]q2; always @(posedge clk) begin if (ld==1) q2 <= d2; end register r0 (clk,ld,d0,q0,so); register r1 ( clk,ld,d1, q1,s1); register r2 ( clk, ld,d2, q2,s2); endmodule endmodule Verilog HDL syntax error at register.v(40) near text "endmodule"  

Your error line number, 40, doesn't match the number of lines in the code you posted. You should use add a comment to the line that throws the error. Now I do notice you have two endmodule statements. You should only have one endmodule statement for a module. You are also still instantiating the module register inside the module register . rberek has told you multiple times that you can't do that. If you don't take the advice from forum members that do this stuff professionally then why bother asking any questions? - - - Updated - - - You know looking at your code some more you don't seem to understand anything about Verilog or how to comment code properly. Comments should tell why you did something and/or what it does somewhere else in the code. Not obvious stuff like "here are the input ports"...how about...// three DFF inputs that are captured by ld on the rising edge of clk Code: module register (clk, ld, d0,d1,d2,q0,q1,q2); input clk; input ld; // Input Port Declarations ---- ads-ee useless comment not even worth typing this input [3:0] d0 ; input [3:0] d1 ; input [3:0] d2 ; // Output Port Declarations ---- ads-ee useless comment not even worth typing this output [3:0] q0; output [3:0] q1; output [3:0] q2; Typical antiquated Verilog 87 method taught to B/M-Tech students when Verilog 2001 port syntax is supported by every single vendor. Code: module register ( input clk, // common D-FF load signal, active high input ld, // D-FF inputs input [3:0] d0, input [3:0] d1, input [3:0] d2, // D-FF outputs output reg [3:0] q0, output reg [3:0] q1, output reg [3:0] q2 ); This is how you do this in Verilog 2001. you don't even use these signals? Code: // ports wire wire [3:0] c0; wire [3:0] c1; wire [3:0] c2; What is with this crazy indenting? Code: reg [3:0]q0; always @(posedge clk) begin if (ld==1) q0 <= d0; end reg [3:0]q1; always @(posedge clk) begin if (ld==1) q1 <= d1; end reg [3:0]q2; always @(posedge clk) begin if (ld==1) q2 <= d2; end Reformated and cleaned up so it's readable. Code: always @(posedge clk) begin if (ld) q0 <= d0; end always @(posedge clk) begin if (ld) q1 <= d1; end always @(posedge clk) begin if (ld) q2 <= d2; end Your trying to instantiate the register module inside itself. This is illegal. Besides that your register instances don't even have the same number of ports as the register module. Code: module [COLOR="#FF0000"]register[/COLOR] (clk, ld, d0,d1,d2,q0,q1,q2); //... [COLOR="#FF0000"]register[/COLOR] r0 (clk,ld,d0,q0,so); [COLOR="#FF0000"]register[/COLOR] r1 ( clk,ld,d1, q1,s1); [COLOR="#FF0000"]register[/COLOR] r2 ( clk, ld,d2, q2,s2); What can I say...there are too many endmodule statements here. Code: endmodule endmodule  

Advanced Member level 5

You are also still instantiating the module register inside the module register. rberek has told you multiple times that you can't do that. If you don't take the advice from forum members that do this stuff professionally then why bother asking any questions? Click to expand...

vead said: when I don't use instantiating the module then I get more error as you said i write code without instantiating the module but tell me why I am getting error Code: module core_v(A,B,Cin,S,Cout); input A, B, Cin; output S, Cout; wire S1, C1, C2; (A, B, S1, C1); (S1, Cin, S, Cout); (Cout, C1, C2); endmodule error Code: Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 0 warnings Error: Peak virtual memory: 230 megabytes Error: Processing ended: Thu Sep 25 10:36:30 2014 Error: Elapsed time: 00:00:05 Error: Total CPU time (on all processors): 00:00:03 Click to expand...

finally I made some code with no error Code: module core_v (clk, ld, d0,q0); // Input Port Declarations input clk; input ld; input [3:0] d0 ; wire [3:0] c0; // Output Port Declarations output [3:0] q0; reg [3:0]q0; always @(posedge clk) begin if (ld==1) q0 <= d0; end endmodule module registerr1(clk,ld,d1,q1); input [3:0] d1 ,clk,ld; output [3:0] q1; wire [3:0] c1; reg [3:0]q1; always @(posedge clk) begin if (ld==1) q1 <= d1; end endmodule module register2 (clk,ld,d2,q2); input [3:0] d2,clk,ld ; output [3:0] q2; wire [3:0] c2; reg [3:0]q2; always @(posedge clk) begin if (ld==1) q2 <= d2; end core_v r0 (clk,ld,d0,q0,s0); core_v r1 (clk,ld,d1q1,s1); core_v r2 (clk,ld,d2,d2,s2); endmodule  

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How Formulas Determine Variable Data Types

Variables can be of these data types: numeric, text or date. The data type determines the type of information the variable holds.

You don't have to specify the variable type. Formulas determine the type based on how you use the variable. For example, if you set a variable to 'J. Smith', the formula interprets it as a text variable.

Determine Variable Data Types

Formulas process the rules that determine the variable data type in the order listed:

The variable can be an input you name in the input statement. For example:

If you don't specify the variable data type in the statement, the formula assumes it's a number.

You can use the DEFAULT_FOR statement to determine the variable data type:

For an array database item, the DEFAULT FOR statement determines the index type and value type:

You can use the DEFAULT_DATA_VALUE FOR statement to determine the variable data type:

The formula searches the list of database items. If the variable is in the list, the data type is known.

If the variable appears in a context handling statement, then the formula searches the list of contexts. If the variable is in the list, then the formula knows the data type, otherwise it returns an error.

If the variable isn't a database item or a context, then the formula treats it as a local variable and determines the data type based on how you use the variable. For example: