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A comprehensive review of processing-in-memory architectures for deep neural networks.
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1. Introduction
1.1. motivation behind review, 1.2. gaps in current research.
- Lack of comprehensive understanding: This review acknowledges the need for a comprehensive understanding of PIM techniques and their potential in revolutionizing deep learning hardware. It provides valuable insights into the advancements in chiplet-based architectures and PIM techniques, emphasizing their benefits in terms of performance, energy efficiency, scalability, and flexibility.
- Limited exploration of chiplet-based architectures: Traditional monolithic chip designs face challenges in scaling up to accommodate the growing sizes of deep learning models. This review highlights chiplet-based architectures as a promising solution to these limitations and discusses their advantages in terms of improved scalability, modularity, and flexibility. It emphasizes the efficient utilization of resources and distribution of computational workload across multiple chiplets for enhanced performance and energy efficiency.
- Insufficient focus on dataflow-awareness and communication optimization: This review recognizes the importance of dataflow-awareness and communication optimization in the design of PIM-enabled manycore architectures. It discusses the tailored dataflow requirements of different machine learning workloads and emphasizes the optimization of PIM architectures to minimize latency and improve energy efficiency. It also addresses the challenges associated with on-chip interconnection networks and the need for scalable communication in chiplet-based architectures.
- Limited exploration of thermal considerations: Thermal constraints pose significant challenges in the design of PIM architectures. This review highlights the importance of thermal considerations and discusses thermally efficient dataflow-aware monolithic 3D NoC architectures for accelerating CNN inferencing. It compares different architectures and emphasizes the advantages of thermally efficient designs, such as TEFLON (thermally efficient dataflow-aware 3D NoC), in terms of energy efficiency, inference accuracy, and thermal resilience.
- Inadequate exploration of programming models and hardware utilization: This review presents a heterogeneous PIM system for energy-efficient neural network training. It addresses the significance of programming models that accommodate both fixed-function logics and programmable cores, providing a unified programming model and runtime system for efficient task offloading and scheduling. It emphasizes achieving balanced hardware utilization in heterogeneous systems with abundant operation-level parallelism.
- Limited analysis of cybersecurity challenges: This review acknowledges the cybersecurity challenges associated with deep neural networks (DNNs) and their increased attack surface. It discusses adversarial attacks, model stealing attacks, and concerns regarding privacy and data leakage. While the focus of this review is primarily on hardware architectures, this section provides an important perspective on the security implications of deploying DNNs.
1.3. Key Insights
1.4. research strategy and data extraction methodology, 2. processing-in-memory (pim), 2.1. introduction, 2.2. challenges.
- Memory organization: PIM requires a rethinking of memory organization to enable processing elements within the memory subsystem. CPUs and GPUs have different memory access patterns and requirements, which need to be accommodated in the design. Efficiently organizing and managing data in a PIM architecture can be complex, especially when dealing with heterogeneous processing units.
- Programming model: PIM architectures require a programming model that allows developers to express data and task parallelism effectively. Developing software for PIM architectures can be challenging due to the need for explicit data placement and synchronization between the CPU and GPU components. The programming models need to be designed to fully exploit the potential parallelism offered by PIM while maintaining ease of use.
- Data movement: Efficient data movement is crucial for PIM architectures. Moving data between the CPU and GPU components can incur significant overhead due to the communication between different memory spaces. Minimizing data movement and optimizing data transfer mechanisms become essential for achieving high performance in heterogeneous CPU–GPU architectures.
- Power and thermal constraints: PIM architectures can potentially consume significant power due to the increased integration of processing elements within the memory subsystem. Managing power and thermal constraints in heterogeneous CPU–GPU architectures is critical to prevent overheating and ensure reliable operation. Designing efficient power management techniques that balance performance and energy consumption is a significant challenge.
- Memory consistency and coherence: Maintaining memory consistency and coherence in PIM architectures is complex, particularly in heterogeneous CPU–GPU systems. CPUs and GPUs often have their own caches and memory hierarchies, which need to be synchronized to ensure data integrity and correctness. Developing efficient coherence protocols and memory consistency models for heterogeneous PIM architectures is a non-trivial task.
- Hardware design and integration: Hardware design challenges arise when integrating processing elements within the memory subsystem. PIM architectures require modifications to the memory controller, cache hierarchy, and interconnects to enable efficient data processing within memory. Co-designing the hardware components and optimizing the integration of processing elements in a heterogeneous CPU–GPU architecture is a significant challenge.
3. PIM-Based Systems
3.1. heterogeneous pim architecture, 3.2. dataflow aware architecture, 3.3. thermally aware architecture, 3.4. processing-in-memory systems applications, 3.4.1. graph neural networks, 3.4.2. nn inference, 4. necessity of cyber security in pim, 5. summary of the review.
- Exploring advanced memory technologies: further investigation into emerging memory technologies, such as memristors or spintronics, can offer new opportunities for enhancing the performance and energy efficiency of PIM architectures.
- Optimizing communication and interconnectivity: continued research on efficient on-chip interconnection networks and communication protocols can further reduce data movement and latency in PIM architectures.
- Integration with emerging technologies: exploring the integration of PIM architectures with other emerging technologies, such as neuromorphic computing or quantum computing, can lead to novel and more efficient computing systems.
- Security and privacy considerations: addressing the cybersecurity challenges associated with deep neural networks and PIM architectures, including adversarial attacks, model stealing attacks, and privacy concerns, is crucial for the widespread adoption of these technologies.
- Hardware–software co-design: further exploration of hardware–software co-design approaches can enable better optimization and utilization of PIM architectures, considering the unique characteristics of deep learning workloads.
- Real-world application deployment: conducting practical experiments and case studies to evaluate the performance, energy efficiency, and scalability of PIM architectures in real-world deep learning applications can provide valuable insights for their adoption.
6. Conclusions
Author contributions, conflicts of interest.
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Click here to enlarge figure
Paper | Approach/Architecture | Description | Key Features | Advantages | Challenges |
---|
[ ] | Hardware Design with 3D Stacked Memory | Integration of fixed-function arithmetic units and programmable cores on a 3D die-stacked memory | Minimizes data movement, improves system performance, programming model and runtime system for offloading and scheduling | | |
[ ] | UPMEM PIM Architecture | DRAM memory arrays combined with in-order cores (DRAM processing units—DPUs) on the same chip | Improves performance and energy efficiency in memory-bound workloads, benchmarking against CPU and GPU counterparts | | |
[ ] | Practical PIM Architecture with Commodity DRAM | Exploits bank-level parallelism in commercial DRAM and 2.5D/3D stacking integration technologies | Higher bandwidth, lower energy per bit transfer, no changes to host processors or application code | | |
[ ] | Lattice Architecture with NVPIM | Utilizes nonvolatile processing-in-memory (NVPIM) based on resistive random-access memory (ReRAM) for accelerating DCNNs | Eliminates analog–digital conversions, reduces data copies/writes, improved energy efficiency and performance | | |
[ ] | PIM-STM Library | Library providing various implementations of transactional memory (TM) for PIM systems | Efficient TM implementation in PIM devices, evaluation of different design choices and algorithms | | |
[ ] | Reconfigurable PIM Architecture | PIM architecture integrated within DRAM sub-arrays, leveraging multi-functional look-up-tables | Higher energy efficiency, programmability, and flexibility for CNN and DNN processing | | |
[ ] | StreamPIM Architecture | Utilizes racetrack memory (RM) techniques and domain-wall nanowires to address memory wall issue | Improved performance and energy efficiency in large-scale applications, tight coupling of memory core and computation units | | |
Paper | Architecture | Challenges | Proposed Solutions |
---|
[ ] | Chiplet-based 2.5D architectures | Communication limitations, energy efficiency, cost advantages | Integration of multiple smaller dies through a network-on-interposer (NoI) |
[ ] | Thermally optimized dataflow-aware monolithic 3D (M3D) NoC architecture | Efficient communication, thermal challenges of ReRAMs | Space-filling curves (SFCs) for dataflow-awareness, avoiding thermal hotspots, distributing high-power consuming cores |
[ ] | ReRAM-based processing-in-memory (PIM) architectures | Model accuracy, performance, noise, hard faults, process variations, limited write endurance | ReRAM-based heterogeneous manycore PIM designs |
[ ] | Network-on-package (NoP) architecture for DL workloads | Communication requirements, fabrication costs | SWAP architecture based on DL traffic characteristics |
[ ] | Mixed-precision RRAM-based compute-in-memory (CIM) architecture | Higher weight precision, ADC resolution | MINT architecture with analog computation inside memory array |
[ ] | Multi-accelerator systems, hardware-mapping co-optimization | Latency, energy consumption, cost | MOHaM framework for multi-objective hardware-mapping co-optimization |
Paper | Methodology | Advantages | Challenges |
---|
[ ] | Heterogeneous chip-lets | | |
[ ] | Deep convolutional neural networks (DCNN) | | -- |
[ ] | Deep learning techniques (LSTMs, DNNs, CNNs) combined with transfer learning | | |
[ ] | Deep neural networks and transfer learning | | -- |
[ ] | Processing-in-memory (PIM) architecture | | |
[ ] | Processing-in-memory (PiM) architectures and timing attacks | -- | |
Paper | Architecture | Challenges | Proposed Solutions | Future Scope |
---|
[ ] | Chiplet-based 2.5D architectures | Communication limitations, energy efficiency, cost advantages | Integration of multiple smaller dies through a network-on-interposer (NoI) | Exploring advanced interconnect technologies, optimizing power efficiency further |
[ ] | Thermally optimized dataflow-aware monolithic 3D (M3D) NoC architecture | Efficient communication, thermal challenges of ReRAMs | Space-filling curves (SFCs) for dataflow-awareness, avoiding thermal hotspots, distributing high-power consuming cores | Investigating advanced thermal management techniques, extending to new memory technologies |
[ ] | ReRAM-based processing-in-memory (PIM) architectures | Model accuracy, performance, noise, hard faults, process variations, limited write endurance | ReRAM-based heterogeneous manycore PIM designs | Enhancing error tolerance, exploring novel training algorithms for PIM architectures |
[ ] | Network-on-package (NoP) architecture for DL workloads | Communication requirements, fabrication costs | SWAP architecture based on DL traffic characteristics | Exploring advanced packaging technologies, optimizing for heterogeneous workloads |
[ ] | Mixed-precision RRAM-based compute-in-memory (CIM) architecture | Higher weight precision, ADC resolution | MINT architecture with analog computation inside memory array | Investigating novel analog computing schemes, optimizing for large-scale deployment |
[ ] | Multi-accelerator systems, hardware-mapping co-optimization | Latency, energy consumption, cost | MOHaM framework for multi-objective hardware-mapping co-optimization | Exploring dynamic workload allocation, optimizing for emerging DL algorithms |
[ ] | TEFLON: A Design Space Exploration Framework for Hardware Accelerators | Design space exploration, accelerator architectures | TEFLON framework for exploring accelerator designs with customizable datapath and memory hierarchy | Enhancing design exploration capabilities, incorporating new architectural innovations |
[ ] | Deep Learning Accelerators: A Comprehensive Survey | Deep learning accelerator architectures, performance, energy efficiency | Survey of various deep learning accelerator architectures and their characteristics | Investigating hardware–software co-design, exploring heterogeneous computing platforms |
[ ] | Efficient Processing of Deep Learning Models: A Tutorial and Survey | Deep learning model compression, quantization, hardware-friendly optimization | Tutorial and survey on various techniques for efficient processing of deep learning models | Exploring federated learning approaches, optimizing for edge and IoT devices |
[ ] | Hardware Architectures for Deep Learning: A Survey | Hardware architectures for deep learning, accelerators, memory systems | Comprehensive survey on hardware architectures for deep learning, including accelerators and memory systems | Investigating neuromorphic computing, exploring advanced memory technologies |
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Kaur, R.; Asad, A.; Mohammadi, F. A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks. Computers 2024 , 13 , 174. https://doi.org/10.3390/computers13070174
Kaur R, Asad A, Mohammadi F. A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks. Computers . 2024; 13(7):174. https://doi.org/10.3390/computers13070174
Kaur, Rupinder, Arghavan Asad, and Farah Mohammadi. 2024. "A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks" Computers 13, no. 7: 174. https://doi.org/10.3390/computers13070174
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Aims and scope. Journal metrics Editorial board. Communication Research Reports publishes original research in the form of brief empirical articles (approximately 3,500 words maximum, and no more than two tables or figures; accepted papers are usually edited to 10 double-spaced pages prior to press) on a variety of topics of human communication.
Explore the current issue of Communication Research Reports, Volume 41, Issue 2, 2024. Browse; Search. Close search. Publish. ... About this journal About. Journal metrics Aims & scope Journal information Editorial board News & calls for papers Advertising information; Browse all articles & issues Browse.
About this journal About. Journal metrics Aims & scope Journal information Editorial board News & calls for papers Advertising information; ... Browse the list of issues and latest articles from Communication Research Reports. All issues Special issues . Latest articles Volume 41 2024 Volume 40 2023 Volume 39 2022 ...
Communication Research (CR), peer-reviewed and published bi-monthly, has provided researchers and practitioners with the most up-to-date, comprehensive and important research on communication and its related fields.It publishes articles that explore the processes, antecedents, and consequences of communication in a broad range of societal systems.
Communication Research Reports is a quarterly peer-reviewed academic journal covering communication studies. It was established in 1984 and is published by Routledge . The journal specializes in the publication of reports-style manuscripts using social scientific methods (such as quantitative data analysis). The most common type of manuscripts ...
Communication Research Reports publishes original research in the form of brief empirical articles (approximately 3,500 words maximum, and no more than two tables or figures; accepted papers are usually edited to 10 double-spaced pages prior to press) on a variety of topics of human communication. Empirical studies in the general contexts of ...
Preview abstract. Restricted access Research article First published March 29, 2023 pp. 580-603. xml GET ACCESS. Table of contents for Communication Research, 51, 5, Jul 01, 2024.
Why you need Communication Research. Research and theory presented in all areas of communication give you comprehensive coverage of the field ; Rigorous, empirical analysis provides you with research that's reliable and high in quality ; The multi-disciplinary perspective contributes to a greater understanding of communication processes and ...
Sage publishes a diverse portfolio of fully Open Access journals in a variety of disciplines. EXPLORE GOLD OPEN ACCESS JOURNALS . Alternatively, you can explore our Disciplines Hubs, including: ... Communication Research ISSN: 0093-6502; Online ISSN: 1552-3810; About Sage; Contact us;
Web-first: Communication Research Reports is a 'web-first' journal: subscribers will have access to the four issues online during the year, and will receive a printed archive volume at the end of the year. Peer Review Policy: Articles appearing in this journal have been screened by the editor and undergone rigorous peer review.
The work on Competence (human resources) addressed in Communication Research Reports expands to the thematically related Credibility. Social psychology (68.76%) Developmental psychology (20.08%) Perception (16.06%) What are the most cited papers published in the journal? Self‐report as an approach to measuring communication competence (296 ...
The ISSN of Communication Research Reports journal is 08824096. An International Standard Serial Number (ISSN) is a unique code of 8 digits. It is used for the recognition of journals, newspapers, periodicals, and magazines in all kind of forms, be it print-media or electronic.
ICA Conferences. ICA holds a large annual conference and smaller regional conferences throughout the year. Learn more. A journal of the International Communication Association, Human Communication Research concentrates on presenting the best empirical work in the area of.
Communication Research is a bimonthly peer-reviewed academic journal that covers the field of communication studies and explores the processes, ... According to the Journal Citation Reports, its 2017 impact factor is 3.391, ranking it 3rd out of 84 journals in the category "Communication". References
Empirical research in communication began in the 20th century, and there are more researchers pursuing answers to communication questions today than at any other time. The editorial goal of Communication Research is to offer a special opportunity for reflection and change in the new millennium. To qualify for publication, research should, first ...
NCA has prepared a list of more than 100 journals that publish scholarship in the discipline of Communication. The list includes the 11 journals published by NCA (in boldface, below), as well as journals published independently or by other associations. NCA does not include on this list journals that have been identified as predatory or pay-to-publish journals. The list is categorized by the ...
Publishes brief empirical articles on communication studies in the context of communication traits, nonverbal, and interpersonal. ... All Journals Communication Research Reports Communication Research Reports Search in: Advanced search Citation search ...
Communication Research Reports publishes original research in the form of brief empirical articles (approximately 3,500 words maximum, and no more than two tables or figures; accepted papers are usually edited to 10 double-spaced pages prior to press) on a variety of topics of human communication.
Angie Chung et al. Article | Published online: 4 Apr 2024. Disclosing Bipolar Disorder in Romantic Relationships. Christina Granato Yoshimura et al. Article | Published online: 2 Apr 2024. View all latest articles. Explore the current issue of Communication Reports, Volume 37, Issue 2, 2024.
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Get access to Communication Research Reports details, impact factor, Journal Ranking, H-Index, ISSN, Citescore, Scimago Journal Rank (SJR). Check top authors, submission guidelines, Acceptance Rate, Review Speed, Scope, Publication Fees, Submission Guidelines at one place. Improve your chances of getting published in Communication Research Reports with Researcher.Life.
All journal articles featured in Communication Research Reports vol 1 issue 1. Log in | Register Cart. Home All Journals Communication Research Reports List of Issues Volume 1, Issue 1 ... Communication Research Reports, Volume 1, Issue 1 (1984)
Activist groups attack animal research and put scientists and their institutions under pressure, whereas scientists often remain silent. We report an interdisciplinary research project driven by a communication science perspective on how citizens respond to news reports about animal research (3 experiments, overall N = 765) and a German science-initiated information platform ("Tierversuche ...
This comprehensive review explores the advancements in processing-in-memory (PIM) techniques and chiplet-based architectures for deep neural networks (DNNs). It addresses the challenges of monolithic chip architectures and highlights the benefits of chiplet-based designs in terms of scalability and flexibility. This review emphasizes dataflow-awareness, communication optimization, and thermal ...
Communication Reports (CR), published quarterly, is one of two scholarly journals of the Western States Communication Association (WSCA). The journal publishes original manuscripts that are short, data/text-based, and related to the broadly defined field of human communication. The mission of the journal is to showcase exemplary scholarship ...